Global Table of Contents

Version 1.1
MIPS Technologies, Inc.
2011 North Shoreline
Mountain View, California 94039-7311
http://www.mips.com
Acknowledgments
About This Manual
Glossary
Stylistic Conventions
Getting MIPS Documents On-Line
1. - Introduction to the R10000 Processor
1.1 - MIPS Instruction Set Architecture (ISA)
1.2 - What is a Superscalar Processor?
Pipeline and Superpipeline Architecture
Superscalar Architecture
1.3 - What is an R10000 Microprocessor?
R10000 Superscalar Pipeline
Instruction Queues
Execution Pipelines
64-bit Integer ALU Pipeline
Load/Store Pipeline
64-bit Floating-Point Pipeline
Functional Units
Primary Instruction Cache (I-cache)
Primary Data Cache (D-cache)
Instruction Decode And Rename Unit
Branch Unit
External Interfaces
1.4 - Instruction Queues
Integer Queue
Floating-Point Queue
Address Queue
1.5 - Program Order and Dependencies
Instruction Dependencies
Execution Order and Stalling
Branch Prediction and Speculative Execution
Resolving Operand Dependencies
Resolving Exception Dependencies
Strong Ordering
An Example of Strong Ordering
1.6 - R10000 Pipelines
Stage 1
Stage 2
Stage 3
Stages 4-6
Floating-Point Multiplier (3-stage Pipeline)
Floating-Point Divide and Square-Root Units
Floating-Point Adder (3-stage Pipeline)
Integer ALU1 (1-stage Pipeline)
Integer ALU2 (1-stage Pipeline)
Address Calculation and Translation in the TLB
1.7 - Implications of R10000 Microarchitecture on Software
Superscalar Instruction Issue
Speculative Execution
Nonblocking Caches
1.8 - R10000-Specific CPU Instructions
PREF
LL/SC
SYNC
1.9 - Performance
User Instruction Latency and Repeat Rate
Other Performance Issues
Cache Performance
2. - System Configurations
2.1 - Uniprocessor Systems
2.2 - Multiprocessor Systems
Multiprocessor Systems Using Dedicated External Agents
Multiprocessor Systems Using a Cluster Bus
3. - Interface Signal Descriptions
3.1 - Power Interface Signals
3.2 - Secondary Cache Interface Signals
3.3 - System Interface Signals
3.4 - Test Interface Signals
4. - Cache Organization and Coherency
4.1 - Primary Instruction Cache
4.2 - Primary Data Cache
4.3 - Secondary Cache
4.4 - Cache Algorithms
Descriptions of the Cache Algorithms
Uncached
Cacheable Noncoherent
Cacheable Coherent Exclusive
Cacheable Coherent Exclusive on Write
Uncached Accelerated
4.5 - Relationship Between Cached and Uncached Operations
4.6 - Cache Algorithms and Processor Requests
4.7 - Cache Block Ownership
5. - Secondary Cache Interface
5.1 - Tag and Data Arrays
5.2 - Secondary Cache Interface Frequencies
5.3 - Secondary Cache Indexing
Indexing the Data Array
Indexing the Tag Array
5.4 - Secondary Cache Way Prediction Table
5.5 - Secondary Cache Tag
SCTag(25:4), Physical Tag
SCTag(3:2), PIdx
SCTag(1:0), Cache Block State
5.6 - Read Sequences
4-Word Read Sequence
8-Word Read Sequence
16 or 32-Word Read Sequence
Tag Read Sequence
5.7 - Write Sequences
4-Word Write Sequence
8-Word Write Sequence
16 or 32-Word Write Sequence
Tag Write Sequence
6. - System Interface Operations
6.1 - Request and Response Cycles
6.2 - System Interface Frequencies
6.3 - Register-to-Register Operation
6.4 - System Interface Signals
6.5 - Master and Slave States
6.6 - Connecting to an External Agent
6.7 - Cluster Bus
6.8 - System Interface Connections
Uniprocessor System
Multiprocessor System Using Dedicated External Agents
Multiprocessor System Using the Cluster Bus
6.9 - System Interface Requests and Responses
Processor Requests
External Responses
External Requests
Processor Responses
Outstanding Requests and Request Numbers
Request and Response Relationship
6.10 - System Interface Buffers
Incoming Buffer
Cached Request Buffer
Outgoing Buffer
Uncached Buffer
Cluster Request Buffer
6.11 - System Interface Flow Control
Processor Write and Eliminate Request Flow Control
Processor Read and Upgrade Request Flow Control
Processor Coherency Data Response Flow Control
External Request Flow Control
External Data Response Flow Control
6.12 - System Interface Block Data Ordering
External Block Data Responses
Processor Coherency Data Responses
Processor Block Write Requests
6.13 - System Interface Bus Encoding
SysCmd[11:0] Encoding
SysCmd[11] Encoding
SysCmd[10:0] Address Cycle Encoding
SysCmd[10:0] Data Cycle Encoding
SysCmd[11:0] Map
SysAD[63:0] Encoding
SysAD[63:0] Address Cycle Encoding
SysAD[63:60]
SysAD[59:58] Uncached Attribute
SysAD[57]
SysAD[56:40]
SysAD[39:0]
SysAD[63:0] Data Cycle Encoding
SysState[2:0] Encoding
SysResp[4:0] Encoding
6.14 - Interrupts
Hardware Interrupts
Software Interrupts
Timer Interrupt
Nonmaskable Interrupt
6.15 - Protocol Abbreviations
6.16 - System Interface Arbitration
System Interface Arbitration Rules
Uniprocessor System
Multiprocessor System Using Cluster Bus
6.17 - System Interface Request and Response Protocol
Processor Request Protocol
Processor Block Read Request Protocol
Processor Double/Single/Partial-Word Read Request Protocol
Processor Block Write Request Protocol
Processor Double/Single/Partial-Word Write Request Protocol
Processor Upgrade Request Protocol
Processor Eliminate Request Protocol
Processor Request Flow Control Protocol
External Response Protocol
External Block Data Response Protocol
External Double/Single/Partial-Word Data Response Protocol
External Completion Response Protocol
External Request Protocol
External Intervention Request Protocol
External Allocate Request Number Request Protocol
External Invalidate Request Protocol
External Interrupt Request Protocol
Processor Response Protocol
Processor Coherency State Response Protocol
Processor Coherency Data Response Protocol
6.18 - System Interface Coherency
External Intervention Shared Request
External Intervention Exclusive Request
External Invalidate Request
External Coherency Request Action
Coherency Conflicts
Internal Coherency Conflicts
External Coherency Conflicts
External Coherency Request Latency
SysGblPerf* Signal
6.19 - Cluster Bus Operation
6.20 - Support for I/O
6.21 - Support for External Duplicate Tags
6.22 - Support for a Directory-Based Coherency Protocol
6.23 - Support for Uncached Attribute
6.24 - Support for Hardware Emulation
7. - Clock Signals
7.1 - System Interface Clock and Internal Processor Clock Domains
7.2 - Secondary Cache Clock
7.3 - Phase-Locked-Loop
8. - Initialization
8.1 - Initialization of Logical Registers
8.2 - Power-On Reset Sequence
8.3 - Cold Reset Sequence
8.4 - Soft Reset Sequence
8.5 - Mode Bits
9. - Error Protection and Handling
9.1 - Correctable Errors
9.2 - Uncorrectable Errors
9.3 - Propagation of Uncorrectable Errors
9.4 - Cache Error Exception
9.5 - CP0 CacheErr Register EW Bit
9.6 - CP0 Status Register DE Bit
9.7 - CACHE Instruction
9.8 - Error Protection Schemes Used by R10000
Parity
Sparse Encoding
ECC
9.9 - Primary Instruction Cache Error Protection and Handling
Error Protection
Error Handling
9.10 - Primary Data Cache Error Protection and Handling
Error Protection
Error Handling
9.11 - Secondary Cache Error Protection and Handling
Error Protection
Error Handling
Data Array
Data Array in Correction Mode
Data Array in Noncorrection Mode
Tag Array
9.12 - System Interface Error Protection and Handling
Error Protection
Error Handling
SysCmd(11:0) Bus
SysAD(63:0) Bus
Processor in Master State
Processor in Slave State
Correctable Error Detected
Uncorrectable Error Detected
SysState(2:0) Bus
SysResp(4:0) Bus
Protocol Observation
10. - CACHE Instructions
10.1 - Notes on CACHE Instruction Operations
Virtual Address
Physical Address
CP0 Not Usable
TLB Refill and TLB Invalid Exceptions on CacheOps
Hit Operation Accesses
Watch Exception
Address Error Exception
Write Back
Invalidation
CE Bit
CH Bit
Serial Operation of CACHE Instructions
Instructions Not Supported
Op Field Encoding
10.2 - Index Invalidate (I)
10.3 - Index WriteBack Invalidate (D)
10.4 - Index WriteBack Invalidate (S)
10.5 - Index Load Tag (I)
10.6 - Index Load Tag (D)
10.7 - Index Load Tag (S)
10.8 - Index Store Tag (I)
10.9 - Index Store Tag (D)
10.10 - Index Store Tag (S)
10.11 - Hit Invalidate (I)
10.12 - Hit Invalidate (D)
10.13 - Hit Invalidate (S)
10.14 - Cache Barrier
10.15 - Hit Writeback Invalidate (D)
10.16 - Hit WriteBack Invalidate (S)
10.17 - Index Load Data (I)
10.18 - Index Load Data (D)
10.19 - Index Load Data (S)
10.20 - Index Store Data (I)
10.21 - Index Store Data (D)
10.22 - Index Store Data (S)
11. - JTAG Interface Operation
11.1 - Test Access Port (TAP)
TAP Controller (Input)
11.2 - Instruction Register
11.3 - Bypass Register
11.4 - Boundary Scan Register
12. - Electrical Specifications
12.1 - DC Electrical Specification
DC Power Supply Levels
DCOk and Power Supply Sequencing
Maximum Operating Conditions
Input Signal Level Sensing
Mode Definitions
Vref[SC,Sys]
Unused Inputs
DC Input/Output Specifications
12.2 - AC Electrical Specification
Maximum Operating Conditions
Test Specification
Secondary Cache and System Interface Timing
Enable/Output Delay, Setup, Hold Time
Asynchronous Inputs
12.3 - Signal Integrity Issues
Reference Voltage
Power Supply Regulation
Maximum Input Voltage Levels
Decoupling Capacitance
Output I-V Curves
Switching and Slew Rate Characteristics
13. - Packaging
13.1 - R10000 Single-Chip Package, 599CLGA
Mechanical Characteristics
Electrical Characteristics
Thermal Characteristics
Assembly Drawings and Pinout List
599CLGA Pinout
14. - Coprocessor 0
14.1 - Index Register (0)
14.2 - Random Register (1)
14.3 - EntryLo0 (2), and EntryLo1 (3) Registers
14.4 - Context (4)
14.5 - PageMask Register (5)
14.6 - Wired Register (6)
14.7 - BadVAddr Register (8)
14.8 - Count and Compare Registers (9 and 11)
14.9 - EntryHi Register (10)
14.10 - Status Register (12)
Status Register Fields
Diagnostic Status Field
Coprocessor Accessibility
14.11 - Cause Register (13)
14.12 - Exception Program Counter (14)
14.13 - Processor Revision Identifier (PRId) Register (15)
14.14 - Config Register (16)
14.15 - Load Linked Address (LLAddr) Register (17)
14.16 - WatchLo (18) and WatchHi (19) Registers
14.17 - XContext Register (20)
14.18 - FrameMask Register (21)
14.19 - Diagnostic Register (22)
14.20 - Performance Counter Registers (25)
14.21 - ECC Register (26)
14.22 - CacheErr Register (27)
CacheErr Register Format for Primary Instruction Cache Errors
CacheErr Register Format for Primary Data Cache Errors
CacheErr Register Format for Secondary Cache Errors
CacheErr Register Format for System Interface Errors
14.23 - TagLo (28) and TagHi (29) Registers
CacheOp is Index Load/Store Tag
Primary Instruction Cache Operation
Primary Data Cache Operation
Secondary Cache Operation
CacheOp is Index Load/Store Data
Primary Instruction Cache Operation
Primary Data Cache Operation
Secondary Cache Operation
14.24 - ErrorEPC Register (30)
14.25 - CP0 Instructions
Hazards
Branch on Coprocessor 0
14.26 - CP0 Move Instructions
14.27 - CACHE Instruction
14.28 - DMFC0 Instruction
14.29 - DMTC0 Instruction
14.30 - ERET Instruction
14.31 - MFC0 Instruction
14.32 - Move To/From the Performance Counter
14.33 - MTC0 Instruction
14.34 - TLBP Instruction
14.35 - TLBR Instruction
14.36 - TLBWI Instruction
14.37 - TLBWR Instruction
15. - Floating-Point Unit
15.1 - Floating Point Unit Operations
15.2 - Floating-Point Unit Control
15.3 - Floating-Point General Registers (FGRs)
32- and 64-Bit Operations
Load and Store Operations
15.4 - Floating-Point Control Registers
Floating-Point Implementation and Revision Register
Floating-Point Status Register (FSR)
Bit Descriptions of the FSR
Loading the FSR
15.5 - FPU Instructions
CVT.L.fmt
Moves and Conditional Moves
CFC1/CTC1
16. - Memory Management
16.1 - Processor Modes
Processor Operating Modes
Addressing Modes
16.2 - Virtual Address Space
User Mode Operations
32-bit User Mode (useg)
64-bit User Mode (xuseg)
Supervisor Mode Operations
32-bit Supervisor Mode, User Space (suseg)
32-bit Supervisor Mode, Supervisor Space (sseg)
64-bit Supervisor Mode, User Space (xsuseg)
64-bit Supervisor Mode, Current Supervisor Space (xsseg)
64-bit Supervisor Mode, Separate Supervisor Space (csseg)
Kernel Mode Operations
32-bit Kernel Mode, User Space (kuseg)
32-bit Kernel Mode, Kernel Space 0 (kseg0)
32-bit Kernel Mode, Kernel Space 1 (kseg1)
32-bit Kernel Mode, Supervisor Space (ksseg)
32-bit Kernel Mode, Kernel Space 3 (kseg3)
64-bit Kernel Mode, User Space (xkuseg)
64-bit Kernel Mode, Current Supervisor Space (xksseg)
64-bit Kernel Mode, Physical Spaces (xkphys)
64-bit Kernel Mode, Kernel Space (xkseg)
64-bit Kernel Mode, Compatibility Spaces (ckseg1:0, cksseg, ckseg3)
Address Space Access Privilege Differences Between the R4400 and R1000
16.3 - Virtual Address Translation
Virtual Pages
Virtual Page Size Encodings
Using the TLB
Cache Algorithm Field
Format of a TLB Entry
Address Translation
Address Space Identification (ASID)
Global Processes (G)
Avoiding TLB Conflict
17. - CPU Exceptions
17.1 - Causing and Returning from an Exception
17.2 - Exception Vector Locations
17.3 - TLB Refill Vector Selection
Priority of Exceptions
Cold Reset Exception
Soft Reset Exception
NMI Exception
Address Error Exception
TLB Exceptions
TLB Refill Exception
TLB Invalid Exception
TLB Modified Exception
Cache Error Exception
Virtual Coherency Exception
Bus Error Exception
Integer Overflow Exception
Trap Exception
System Call Exception
Breakpoint Exception
Reserved Instruction Exception
Coprocessor Unusable Exception
Floating-Point Exception
Watch Exception
Interrupt Exception
17.4 - MIPSIV Instructions
17.5 - COP0 Instructions
17.6 - COP1 Instructions
17.7 - COP2 Instructions
18. - Cache Test Mode
18.1 - Interface Signals
18.2 - System Interface Clock Divisor
18.3 - Entering Cache Test Mode
18.4 - Exit Sequence
18.5 - SysAD(63:0) Encoding
18.6 - Cache Test Mode Protocol
Normal Write Protocol
Auto-Increment Write Protocol
Normal Read Protocol
Auto-Increment Read Protocol
Glossary
A.1 - Superscalar Processor
A.2 - Pipeline
A.3 - Pipeline Latency
A.4 - Pipeline Repeat Rate
A.5 - Out-of-Order Execution
A.6 - Dynamic Scheduling
A.7 - Instruction Fetch, Decode, Issue, Execution, Completion, and Graduation
A.8 - Active List
A.9 - Free List and Busy Registers
A.10 - Register Renaming
A.11 - Nonblocking Loads and Stores
A.12 - Speculative Branching
A.13 - Logical and Physical Registers
A.14 - Register Files
A.15 - ANDES Architecture

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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